Introduction of embedded development PCB via
Author:He Yu Time:2021-06-07 12:26 Browse(611)
Introduction of embedded development PCB via, touch screen and OLED Forum
Via is an important part of Multilayer PCB, and the cost of drilling usually accounts for 30% to 40% of the cost of PCB manufacturing. In short, every hole in PCB can be called via.
from the perspective of function.

Introduction of embedded development PCB via

vias can be divided into two categories: one is used for electrical connection between layers; the other is used for electrical connection between layers; Secondly, it is used to fix or position the device.
this paper introduces the structure of the device0 w# y3 A- f/ N3 i4 {5 \- v9 K/ xIn terms of process,
these vias are generally divided into three categories, namely blind via, buried via and through via.
the blind vias are located on the top and bottom surface of the printed circuit board.
they have a certain depth and are used to connect the surface circuit with the inner circuit below, The depth of the hole usually does not exceed a certain ratio (aperture).
the buried hole refers to the connecting hole located in the inner layer of the printed circuit board.
it does not extend to the surface of the printed circuit board.
the above two types of holes are located in the inner layer of the printed circuit board.
the through hole forming process is used before lamination, In the process of via formation, several inner layers may be overlapped.
the third kind is called through hole.
this kind of hole passes through the whole circuit board and can be used to realize internal interconnection or as the installation and positioning hole of components.
because the through hole is easier to realize in process.
the cost is lower, so it is used in most printed circuit boards, However, the other two vias are not needed.
the vias mentioned below are considered as vias unless otherwise specified.
8 {% a: G8 x * u'm! v! N8 c! @ 4 K1 Z + T / E) s * r &] from a design point of view.
from a design point of viewA via is mainly composed of two parts, one is the drill hole in the middle, and the other is the pad area around the drill hole.
the size of these two parts determines the size of the via.
obviously.
in high-speed and high-density PCB design, designers always hope that the smaller the via is, the better, so that more wiring space can be left on the board, The smaller the parasitic capacitance, the more suitable it is for high-speed circuits.
however, the smaller the hole size, the higher the cost.
moreover, the size of the via can not be reduced unlimited, which is limited by drilling and plating technology: the smaller the hole is, the longer the drilling time is, and the easier it is to deviate from the center position; And when the depth of the hole is more than 6 times of the diameter of the hole, it is impossible to ensure that the hole wall can be evenly plated with copper.
for example,
now the thickness of a normal 6-layer PCB (through hole depth) is about 50 Mil, so the minimum diameter of the hole that PCB manufacturers can provide can only reach 8 mil, If it is known that the diameter of isolation hole of via on the floor is D2, the diameter of via pad is D1, the thickness of PCB is t, and the dielectric constant of substrate is 0 ε, The parasitic capacitance of the via is approximately C=1.41 ε TD1/(D2-D1)8 t- l0 W, y, G2 Y    K( q& j) e) ? 4 x+ b1 d8 z* U) t- [The main effect of parasitic capacitance of vias on the circuit is to prolong the rise time of the signal and reduce the speed of the circuit.
for example,
for a PCB with a thickness of 50 Mil, if the inner diameter is 10 mil, the parasitic capacitance of vias will affect the circuit,If the diameter of pad is 20MIL and the distance between pad and copper area is 32mil, we can approximately calculate the parasitic capacitance of via by the above formula: C=1.41x4.4x0.050x0.020 / (0.032-0.020)=0.517pf, and the rise time variation caused by this capacitance is: t10-90=2.2c (Z0 / 2)=2.2x0.517x (55 / 2)=31.28ps, Although the effect of the slow rise caused by the parasitic capacitance of a single via is not obvious, the designer should consider it carefully if the vias are used repeatedly to switch between layers; C3 j8 P* f/ P& w* I)| 0 V9 m'm # D. @ "t" @ third, the parasitic inductance of the via is the same.
the parasitic capacitance and the parasitic inductance exist in the via, The parasitic inductance of the via often brings more harm than the parasitic capacitance.
its parasitic series inductance will weaken the contribution of the bypass capacitance.
it will weaken the filtering effect of the whole power system.
we can use the following formula to simply calculate the parasitic inductance of a via: l=5.08h [ln (4h / D) + 1], where l is the inductance of the via.
H is the length of the via, D is the diameter of the central hole.
it can be seen from the formula that the diameter of the through hole has little influence on the inductance, while the length of the through hole has the greatest influence on the inductance.
the above example is still used.
the inductance of the through hole can be calculated as: l=5.08x0.050 [ln (4x0.050 / 0.010) + 1]=1.015nh,The equivalent impedance is XL=π L/T10-90=3.19 Ω. it should be noted that the bypass capacitor needs to pass through two vias when connecting the power layer and the formation, so the parasitic inductance of the vias will be doubled. we can see that in high-speed PCB design, seemingly simple vias often bring a lot of negative effects to circuit design.
in this paper, we analyze the vias parasitic characteristics of high-speed PCB4 b' p    U( w* u- ?$ S1 K/ A0 K( ]( M2 k3 I7 lIn order to reduce the adverse effects caused by the parasitic effect of vias.
in the design, we can try our best to achieve:% k% R9 D "f # y6 S9 X /} 9 U- W! a# o( }1 e, P' W6 \1. Considering the cost and signal quality, select the reasonable size of via.
for example, for the PCB design of 6-10 layer memory module,
it is better to select 10 / 20 mil (drill / pad) via, for some high-density small-size boards, We can also try to use 8 / 18mil vias.
under the current technical conditions, it is difficult to use smaller vias.
for power or ground vias, we can consider using larger vias.
to reduce the impedance   y2 k* z5 M2 W+ @   {: E! M "Q & E: |: I8 L8 Q 2. The two formulas discussed above can be obtained.
the results are as followsUsing thinner PCB is beneficial to reduce the two parasitic parameters of vias.
the results show that the thickness of PCB is lower than the thickness of vias. `2 [" x/ _ 8 B0 d.
^1 D3 y4 t7 m* @" X2 b. n5 R    X (C 3) try not to change the layer of signal wiring on PCB, that is, try not to use unnecessary vias.
% y + m! d) |& z: _- O4 a0 a "i5 V: n: F. B $P. C - M6 x (K 4, the pins of power supply and ground should be drilled nearby.
the shorter the lead between the via and the pin, the better, because they will increase the inductance.
at the same time, the lead of power supply and ground should be as thick as possible.
to reduce the impedance.
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l/ t0 A9 I. C9 ~ 3 d0 P, G8 B5. Place some grounding vias near the vias of the signal layer, so as to provide the nearest circuit for the signal.
even a large number of redundant grounding vias can be placed on the PCB board.
of course.
it needs to be flexible in the design.
the vias model discussed in the front is the case that each layer has pads.
sometimes, We can reduce or even remove the pad of some layers.
especially when the via density is very high.
it may lead to the formation of a cut-off groove in the copper layer. To solve this problem, in addition to moving the position of the via, we can also consider reducing the pad size of the via in the copper layer.
for more information, you can log in to the official website of jiepei PCB: www.jiepei.com/G1562 M6 G& |% [6 R" S4 V.
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